OK3588-C-common.dtsi 30 KB

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  1. #include "dt-bindings/usb/pd.h"
  2. #include <dt-bindings/gpio/gpio.h>
  3. #include <dt-bindings/pwm/pwm.h>
  4. #include <dt-bindings/pinctrl/rockchip.h>
  5. #include <dt-bindings/input/rk-input.h>
  6. #include <dt-bindings/display/drm_mipi_dsi.h>
  7. #include <dt-bindings/display/rockchip_vop.h>
  8. #include <dt-bindings/sensor-dev.h>
  9. #include "rk3588.dtsi"
  10. #include "FET3588-C.dtsi"
  11. #include "rk3588-rk806-single.dtsi"
  12. #include "OK3588-C-Camera.dtsi"
  13. / {
  14. aliases {
  15. mmc0 = &sdhci;
  16. mmc1 = &sdmmc;
  17. };
  18. forlinx-control {
  19. /***
  20. * hdmi0 and edp0 share same port, only one can be used.
  21. * hdmi1 and edp1 share same port, only one can be used.
  22. * only four VPs internally, so up to four interfaces can be activated
  23. * hdmi edp dp can only be displayed on VP0 or VP1 or VP2.
  24. * dsi0 dsi1 can only be displayed on VP2 or VP3.
  25. * rgb can only be displayed on VP3.
  26. *
  27. ***/
  28. /*** if "disabled" , display is controlled by uboot ***/
  29. status = "okay";
  30. HDMI0 = "VP0";
  31. // HDMI1 = "OFF";
  32. // EDP0 = "OFF";
  33. // EDP1 = "VP1";
  34. // DP0 = "OFF";
  35. // DP1 = "OFF";
  36. // MIPI0 = "VP2";
  37. // MIPI1 = "VP3";
  38. // RGB = "OFF";
  39. primary_display = "HDMI0";
  40. primary_display_resolution = "1920x1080p60";
  41. disp_type = "sync";
  42. };
  43. reserved-memory {
  44. #address-cells = <2>;
  45. #size-cells = <2>;
  46. ranges;
  47. dma_trans: dma-trans@3c000000 {
  48. reg = <0x0 0x3c000000 0x0 0x04000000>;
  49. };
  50. /* Reserve 256MB memory for hdmirx-controller@fdee0000 */
  51. cma {
  52. compatible = "shared-dma-pool";
  53. reusable;
  54. reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>;
  55. linux,cma-default;
  56. };
  57. };
  58. /*
  59. fan: pwm-fan {
  60. compatible = "pwm-fan";
  61. #cooling-cells = <2>;
  62. pwms = <&pwm2 0 50000 0>;
  63. };
  64. */
  65. vcc5v0_sys: vcc5v0-sys {
  66. compatible = "regulator-fixed";
  67. regulator-name = "vcc5v0_sys";
  68. regulator-always-on;
  69. regulator-boot-on;
  70. regulator-min-microvolt = <5000000>;
  71. regulator-max-microvolt = <5000000>;
  72. vin-supply = <&vcc12v_dcin>;
  73. };
  74. vbus5v0_typec0: vbus5v0-typec0 {
  75. compatible = "regulator-fixed";
  76. regulator-name = "vbus5v0_typec0";
  77. regulator-min-microvolt = <5000000>;
  78. regulator-max-microvolt = <5000000>;
  79. enable-active-high;
  80. gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
  81. vin-supply = <&vcc5v0_sys>;
  82. pinctrl-names = "default";
  83. pinctrl-0 = <&typec5v_pwren0>;
  84. };
  85. vbus5v0_typec1: vbus5v0-typec1 {
  86. compatible = "regulator-fixed";
  87. regulator-name = "vbus5v0_typec1";
  88. regulator-min-microvolt = <5000000>;
  89. regulator-max-microvolt = <5000000>;
  90. enable-active-high;
  91. gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
  92. vin-supply = <&vcc5v0_sys>;
  93. pinctrl-names = "default";
  94. pinctrl-0 = <&typec5v_pwren1>;
  95. };
  96. vcc3v3_sys: vcc3v3-sys {
  97. compatible = "regulator-fixed";
  98. regulator-name = "vcc3v3_sys";
  99. regulator-always-on;
  100. regulator-boot-on;
  101. regulator-min-microvolt = <3300000>;
  102. regulator-max-microvolt = <3300000>;
  103. vin-supply = <&vcc5v0_sys>;
  104. };
  105. vcc1v8_sys: vcc1v8-sys {
  106. compatible = "regulator-fixed";
  107. regulator-name = "vcc1v8_sys";
  108. regulator-always-on;
  109. regulator-boot-on;
  110. regulator-min-microvolt = <1800000>;
  111. regulator-max-microvolt = <1800000>;
  112. vin-supply = <&vcc3v3_sys>;
  113. };
  114. vcc3v3_pcie30: vcc3v3_pcie30 {
  115. compatible = "regulator-fixed";
  116. regulator-name = "vcc3v3_pcie30";
  117. regulator-boot-on;
  118. regulator-always-on;
  119. regulator-min-microvolt = <3300000>;
  120. regulator-max-microvolt = <3300000>;
  121. vin-supply = <&vcc5v0_sys>;
  122. };
  123. vcc3v3_pcie20: vcc3v3-pcie20 {
  124. compatible = "regulator-fixed";
  125. regulator-name = "vcc3v3-pcie20";
  126. regulator-boot-on;
  127. regulator-always-on;
  128. regulator-min-microvolt = <3300000>;
  129. regulator-max-microvolt = <3300000>;
  130. vin-supply = <&vcc5v0_sys>;
  131. };
  132. vcc3v3_sdmmc: vcc3v3-sdmmc {
  133. compatible = "regulator-fixed";
  134. regulator-name = "vcc3v3_sdmmc";
  135. regulator-min-microvolt = <3300000>;
  136. regulator-max-microvolt = <3300000>;
  137. enable-active-high;
  138. regulator-boot-on;
  139. regulator-always-on;
  140. gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>;
  141. startup-delay-us = <5000>;
  142. vin-supply = <&vcc5v0_sys>;
  143. };
  144. vcc_5g: vcc-5g {
  145. compatible = "regulator-fixed";
  146. regulator-name = "vcc_5g_rst";
  147. regulator-min-microvolt = <1800000>;
  148. regulator-max-microvolt = <1800000>;
  149. enable-active-low;
  150. regulator-boot-on;
  151. regulator-always-on;
  152. gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
  153. startup-delay-us = <5000>;
  154. vin-supply = <&vcc5v0_sys>;
  155. pinctrl-names = "default";
  156. pinctrl-0 = <&net_m2_rst_gpio>;
  157. };
  158. bt_wake: bt-wake {
  159. compatible = "regulator-fixed";
  160. regulator-name = "bt_wake";
  161. regulator-min-microvolt = <1800000>;
  162. regulator-max-microvolt = <1800000>;
  163. enable-active-high;
  164. regulator-boot-on;
  165. regulator-always-on;
  166. gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
  167. vin-supply = <&vcc5v0_sys>;
  168. };
  169. dsi0_en: dsi0-en {
  170. compatible = "regulator-fixed";
  171. pinctrl-names = "default";
  172. pinctrl-0 = <&mipi0_enable_gpio>;
  173. regulator-name = "dsi0_en";
  174. regulator-min-microvolt = <1800000>;
  175. regulator-max-microvolt = <1800000>;
  176. enable-active-high;
  177. regulator-boot-on;
  178. regulator-always-on;
  179. gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
  180. vin-supply = <&vcc5v0_sys>;
  181. };
  182. dsi1_en: dsi1-en {
  183. compatible = "regulator-fixed";
  184. pinctrl-names = "default";
  185. pinctrl-0 = <&mipi1_enable_gpio>;
  186. regulator-name = "dsi1_en";
  187. regulator-min-microvolt = <1800000>;
  188. regulator-max-microvolt = <1800000>;
  189. enable-active-high;
  190. regulator-boot-on;
  191. regulator-always-on;
  192. gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
  193. vin-supply = <&vcc5v0_sys>;
  194. };
  195. adc_keys: adc-keys {
  196. compatible = "adc-keys";
  197. io-channels = <&saradc 1>;
  198. io-channel-names = "buttons";
  199. keyup-threshold-microvolt = <1800000>;
  200. poll-interval = <100>;
  201. vol-up-key {
  202. label = "volume up";
  203. linux,code = <KEY_VOLUMEUP>;
  204. press-threshold-microvolt = <17000>;
  205. };
  206. vol-down-key {
  207. label = "volume down";
  208. linux,code = <KEY_VOLUMEDOWN>;
  209. press-threshold-microvolt = <417000>;
  210. };
  211. menu-key {
  212. label = "menu";
  213. linux,code = <KEY_MENU>;
  214. press-threshold-microvolt = <890000>;
  215. };
  216. back-key {
  217. label = "back";
  218. linux,code = <KEY_BACK>;
  219. press-threshold-microvolt = <1235000>;
  220. };
  221. };
  222. backlight_dsi0: backlight-dsi0 {
  223. compatible = "pwm-backlight";
  224. pwms = <&pwm5 0 25000 0>;
  225. status = "okay";
  226. brightness-levels = <
  227. 0 20 20 21 21 22 22 23
  228. 23 24 24 25 25 26 26 27
  229. 27 28 28 29 29 30 30 31
  230. 31 32 32 33 33 34 34 35
  231. 35 36 36 37 37 38 38 39
  232. 40 41 42 43 44 45 46 47
  233. 48 49 50 51 52 53 54 55
  234. 56 57 58 59 60 61 62 63
  235. 64 65 66 67 68 69 70 71
  236. 72 73 74 75 76 77 78 79
  237. 80 81 82 83 84 85 86 87
  238. 88 89 90 91 92 93 94 95
  239. 96 97 98 99 100 101 102 103
  240. 104 105 106 107 108 109 110 111
  241. 112 113 114 115 116 117 118 119
  242. 120 121 122 123 124 125 126 127
  243. 128 129 130 131 132 133 134 135
  244. 136 137 138 139 140 141 142 143
  245. 144 145 146 147 148 149 150 151
  246. 152 153 154 155 156 157 158 159
  247. 160 161 162 163 164 165 166 167
  248. 168 169 170 171 172 173 174 175
  249. 176 177 178 179 180 181 182 183
  250. 184 185 186 187 188 189 190 191
  251. 192 193 194 195 196 197 198 199
  252. 200 201 202 203 204 205 206 207
  253. 208 209 210 211 212 213 214 215
  254. 216 217 218 219 220 221 222 223
  255. 224 225 226 227 228 229 230 231
  256. 232 233 234 235 236 237 238 239
  257. 240 241 242 243 244 245 246 247
  258. 248 249 250 251 252 253 254 255
  259. >;
  260. default-brightness-level = <200>;
  261. is-forlinx;
  262. };
  263. backlight_dsi1: backlight-dsi1 {
  264. compatible = "pwm-backlight";
  265. pwms = <&pwm6 0 25000 0>;
  266. status = "okay";
  267. brightness-levels = <
  268. 0 20 20 21 21 22 22 23
  269. 23 24 24 25 25 26 26 27
  270. 27 28 28 29 29 30 30 31
  271. 31 32 32 33 33 34 34 35
  272. 35 36 36 37 37 38 38 39
  273. 40 41 42 43 44 45 46 47
  274. 48 49 50 51 52 53 54 55
  275. 56 57 58 59 60 61 62 63
  276. 64 65 66 67 68 69 70 71
  277. 72 73 74 75 76 77 78 79
  278. 80 81 82 83 84 85 86 87
  279. 88 89 90 91 92 93 94 95
  280. 96 97 98 99 100 101 102 103
  281. 104 105 106 107 108 109 110 111
  282. 112 113 114 115 116 117 118 119
  283. 120 121 122 123 124 125 126 127
  284. 128 129 130 131 132 133 134 135
  285. 136 137 138 139 140 141 142 143
  286. 144 145 146 147 148 149 150 151
  287. 152 153 154 155 156 157 158 159
  288. 160 161 162 163 164 165 166 167
  289. 168 169 170 171 172 173 174 175
  290. 176 177 178 179 180 181 182 183
  291. 184 185 186 187 188 189 190 191
  292. 192 193 194 195 196 197 198 199
  293. 200 201 202 203 204 205 206 207
  294. 208 209 210 211 212 213 214 215
  295. 216 217 218 219 220 221 222 223
  296. 224 225 226 227 228 229 230 231
  297. 232 233 234 235 236 237 238 239
  298. 240 241 242 243 244 245 246 247
  299. 248 249 250 251 252 253 254 255
  300. >;
  301. default-brightness-level = <200>;
  302. is-forlinx;
  303. };
  304. edp1-panel {
  305. compatible = "simple-panel";
  306. prepare-delay-ms = <120>;
  307. enable-delay-ms = <120>;
  308. unprepare-delay-ms = <120>;
  309. disable-delay-ms = <120>;
  310. //backlight = <&backlight_edp1>;
  311. width-mm = <254>;
  312. height-mm = <169>;
  313. //enable-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
  314. status = "disabled";
  315. port {
  316. panel_in_edp1: endpoint {
  317. remote-endpoint = <&edp_out_panel>;
  318. };
  319. };
  320. };
  321. /*
  322. backlight_edp1: backlight-edp1 {
  323. compatible = "pwm-backlight";
  324. pwms = <&pwm4 0 20000 0>;
  325. brightness-levels = <
  326. 0 20 20 21 21 22 22 23
  327. 23 24 24 25 25 26 26 27
  328. 27 28 28 29 29 30 30 31
  329. 31 32 32 33 33 34 34 35
  330. 35 36 36 37 37 38 38 39
  331. 40 41 42 43 44 45 46 47
  332. 48 49 50 51 52 53 54 55
  333. 56 57 58 59 60 61 62 63
  334. 64 65 66 67 68 69 70 71
  335. 72 73 74 75 76 77 78 79
  336. 80 81 82 83 84 85 86 87
  337. 88 89 90 91 92 93 94 95
  338. 96 97 98 99 100 101 102 103
  339. 104 105 106 107 108 109 110 111
  340. 112 113 114 115 116 117 118 119
  341. 120 121 122 123 124 125 126 127
  342. 128 129 130 131 132 133 134 135
  343. 136 137 138 139 140 141 142 143
  344. 144 145 146 147 148 149 150 151
  345. 152 153 154 155 156 157 158 159
  346. 160 161 162 163 164 165 166 167
  347. 168 169 170 171 172 173 174 175
  348. 176 177 178 179 180 181 182 183
  349. 184 185 186 187 188 189 190 191
  350. 192 193 194 195 196 197 198 199
  351. 200 201 202 203 204 205 206 207
  352. 208 209 210 211 212 213 214 215
  353. 216 217 218 219 220 221 222 223
  354. 224 225 226 227 228 229 230 231
  355. 232 233 234 235 236 237 238 239
  356. 240 241 242 243 244 245 246 247
  357. 248 249 250 251 252 253 254 255
  358. >;
  359. default-brightness-level = <200>;
  360. };
  361. */
  362. nau8822_sound: nau8822-sound {
  363. status = "okay";
  364. compatible = "rockchip,multicodecs-card";
  365. rockchip,card-name = "rockchip-nau8822";
  366. hp-det-gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
  367. io-channels = <&saradc 3>;
  368. io-channel-names = "adc-detect";
  369. keyup-threshold-microvolt = <1800000>;
  370. poll-interval = <100>;
  371. // spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
  372. // hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
  373. rockchip,format = "i2s";
  374. rockchip,mclk-fs = <256>;
  375. rockchip,cpu = <&i2s0_8ch>;
  376. rockchip,codec = <&nau8822>;
  377. rockchip,audio-routing =
  378. "Headphone", "RHP",
  379. "Headphone", "LHP",
  380. "Speaker", "LSPK",
  381. "Speaker", "RSPK",
  382. "RMICP", "Main Mic",
  383. "RMICN", "Main Mic",
  384. "RMICP", "Headset Mic",
  385. "RMICN", "Headset Mic",
  386. "LMICP", "Main Mic",
  387. "LMICN", "Main Mic",
  388. "LMICP", "Headset Mic",
  389. "LMICN", "Headset Mic";
  390. pinctrl-names = "default";
  391. pinctrl-0 = <&hp_det>;
  392. play-pause-key {
  393. label = "playpause";
  394. linux,code = <KEY_PLAYPAUSE>;
  395. press-threshold-microvolt = <2000>;
  396. poll-interval = <1000>;
  397. };
  398. };
  399. hdmi0_sound: hdmi0-sound {
  400. status = "okay";
  401. compatible = "rockchip,hdmi";
  402. rockchip,mclk-fs = <128>;
  403. rockchip,card-name = "rockchip-hdmi0";
  404. rockchip,cpu = <&i2s5_8ch>;
  405. rockchip,codec = <&hdmi0>;
  406. rockchip,jack-det;
  407. };
  408. dp0_sound: dp0-sound {
  409. status = "okay";
  410. compatible = "rockchip,hdmi";
  411. rockchip,card-name= "rockchip,dp0";
  412. rockchip,mclk-fs = <512>;
  413. rockchip,cpu = <&spdif_tx2>;
  414. rockchip,codec = <&dp0 1>;
  415. rockchip,jack-det;
  416. };
  417. dp1_sound: dp1-sound {
  418. status = "okay";
  419. compatible = "rockchip,hdmi";
  420. rockchip,card-name= "rockchip,dp1";
  421. rockchip,mclk-fs = <512>;
  422. rockchip,cpu = <&spdif_tx5>;
  423. rockchip,codec = <&dp1 1>;
  424. rockchip,jack-det;
  425. };
  426. hdmiin-sound {
  427. compatible = "rockchip,hdmi";
  428. rockchip,mclk-fs = <128>;
  429. rockchip,format = "i2s";
  430. rockchip,bitclock-master = <&hdmirx_ctrler>;
  431. rockchip,frame-master = <&hdmirx_ctrler>;
  432. rockchip,card-name = "rockchip,hdmiin";
  433. rockchip,cpu = <&i2s7_8ch>;
  434. rockchip,codec = <&hdmirx_ctrler 0>;
  435. rockchip,jack-det;
  436. };
  437. test-power {
  438. status = "okay";
  439. };
  440. };
  441. &spdif_tx2 {
  442. status = "okay";
  443. };
  444. &spdif_tx5 {
  445. status = "okay";
  446. };
  447. &pinctrl {
  448. m2 {
  449. net_m2_rst_gpio: net_m2_rst_gpio {
  450. rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
  451. };
  452. };
  453. bt {
  454. bluetooth_wake_pin: bluetooth-wake-pin {
  455. rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
  456. };
  457. };
  458. tf {
  459. sdmmc_pwren_gpio: sdmmc-pwren-gpio {
  460. rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
  461. };
  462. };
  463. lcd {
  464. mipi0_enable_gpio: mipi0-enable-gpio {
  465. rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
  466. };
  467. mipi1_enable_gpio: mipi1-enable-gpio {
  468. rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
  469. };
  470. };
  471. tp_int {
  472. ft5x06_dsi1_gpio: ft5x06-dsi1-gpio {
  473. rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
  474. };
  475. ft5x06_dsi2_gpio: ft5x06-dsi2-gpio {
  476. rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
  477. };
  478. gt911_dsi1_gpio:gt911-dsi0-gpio {
  479. rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
  480. <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
  481. };
  482. gt911_dsi2_gpio:gt911-dsi1-gpio {
  483. rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
  484. <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
  485. };
  486. };
  487. hdmirxdet {
  488. hdmirx_det_gpio: hdmirx-det-gpio {
  489. rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
  490. };
  491. };
  492. extio {
  493. extio_int_gpio: extio-int-gpio {
  494. rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
  495. };
  496. };
  497. usb {
  498. vcc5v0_host_en: vcc5v0-host-en {
  499. rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
  500. };
  501. };
  502. usb-typec {
  503. usbc0_int: usbc0-int {
  504. rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
  505. };
  506. typec5v_pwren0: typec5v-pwren0 {
  507. rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
  508. };
  509. usbc1_int: usbc1-int {
  510. rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
  511. };
  512. typec5v_pwren1: typec5v-pwren1 {
  513. rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
  514. };
  515. };
  516. headphone {
  517. hp_det: hp-det {
  518. rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
  519. };
  520. };
  521. };
  522. &uart4 {
  523. pinctrl-names = "default";
  524. pinctrl-0 = <&uart4m0_xfer>;
  525. status = "okay";
  526. };
  527. &uart6 {
  528. pinctrl-0 = <&uart6m1_xfer>, <&uart6m1_ctsn>, <&uart6m1_rtsn>;
  529. status = "okay";
  530. };
  531. &uart7 {
  532. pinctrl-names = "default";
  533. pinctrl-0 = <&uart7m1_xfer>;
  534. status = "okay";
  535. };
  536. &uart9 {
  537. pinctrl-names = "default";
  538. pinctrl-0 = <&uart9m2_xfer>;
  539. status = "okay";
  540. };
  541. &can1 {
  542. pinctrl-0 = <&can1m1_pins>;
  543. status = "okay";
  544. assigned-clocks = <&cru CLK_CAN1>;
  545. assigned-clock-rates = <200000000>;
  546. };
  547. &can2 {
  548. status = "okay";
  549. assigned-clocks = <&cru CLK_CAN2>;
  550. assigned-clock-rates = <200000000>;
  551. };
  552. &dp0 {
  553. status = "disabled";
  554. };
  555. &dp0_in_vp2 {
  556. status = "disabled";
  557. };
  558. &mdio0 {
  559. rgmii_phy0: phy@1 {
  560. compatible = "ethernet-phy-ieee802.3-c22";
  561. reg = <0x1>;
  562. };
  563. };
  564. &mdio1 {
  565. rgmii_phy1: phy@1 {
  566. compatible = "ethernet-phy-ieee802.3-c22";
  567. reg = <0x2>;
  568. };
  569. };
  570. &gmac0 {
  571. /* Use rgmii-rxid mode to disable rx delay inside Soc */
  572. phy-mode = "rgmii-rxid";
  573. clock_in_out = "output";
  574. snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
  575. snps,reset-active-low;
  576. /* Reset time is 20ms, 100ms for rtl8211f */
  577. snps,reset-delays-us = <0 20000 100000>;
  578. pinctrl-names = "default";
  579. pinctrl-0 = <&gmac0_miim
  580. &gmac0_tx_bus2
  581. &gmac0_rx_bus2
  582. &gmac0_rgmii_clk
  583. &gmac0_rgmii_bus>;
  584. tx_delay = <0x44>;
  585. /* rx_delay = <0x4f>; */
  586. phy-handle = <&rgmii_phy0>;
  587. status = "okay";
  588. };
  589. &gmac1 {
  590. /* Use rgmii-rxid mode to disable rx delay inside Soc */
  591. phy-mode = "rgmii-rxid";
  592. clock_in_out = "output";
  593. snps,reset-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
  594. snps,reset-active-low;
  595. /* Reset time is 20ms, 100ms for rtl8211f */
  596. snps,reset-delays-us = <0 20000 100000>;
  597. pinctrl-names = "default";
  598. pinctrl-0 = <&gmac1_miim
  599. &gmac1_tx_bus2
  600. &gmac1_rx_bus2
  601. &gmac1_rgmii_clk
  602. &gmac1_rgmii_bus>;
  603. tx_delay = <0x44>;
  604. /* rx_delay = <0x4f>; */
  605. phy-handle = <&rgmii_phy1>;
  606. status = "okay";
  607. };
  608. &i2c2 {
  609. status = "okay";
  610. extio: tca6424@23 {
  611. compatible = "ti,tca6424";
  612. reg = <0x23>;
  613. interrupt-parent = <&gpio1>;
  614. interrupts = <RK_PA4 IRQ_TYPE_EDGE_FALLING>;
  615. gpio-controller;
  616. pinctrl-0 = <&extio_int_gpio>;
  617. pinctrl-names = "default";
  618. #gpio-cells = <2>;
  619. status = "okay";
  620. };
  621. ft5x06_dsi0: ft5x06@38 { //dsi0 tp
  622. compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
  623. reg = <0x38>;
  624. // pinctrl-names = "ft5x06_defaults";
  625. // pinctrl-0 = <&ft5x06_dsi1_gpio>;
  626. // interrupt-parent = <&gpio3>;
  627. // interrupts = <RK_PC0 IRQ_TYPE_EDGE_FALLING>;
  628. // irq-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
  629. touchscreen-size-x = <1024>;
  630. touchscreen-size-y = <600>;
  631. status = "disabled";
  632. };
  633. gt9xx_dsi0: gt9xx@14 {
  634. compatible = "goodix,gt911";
  635. reg = <0x14>;
  636. //pinctrl-names = "gt9xx_default";
  637. //pinctrl-0 = <&gt911_dsi1_gpio>;
  638. //interrupt-parent = <&gpio3>;
  639. //interrupts = <RK_PC0 IRQ_TYPE_EDGE_FALLING>;
  640. //irq-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
  641. reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
  642. touchscreen-size-x = <1024>;
  643. touchscreen-size-y = <600>;
  644. is-mutex;
  645. filter-reg = <0x38>;
  646. bus-reg = <0x02>;
  647. status = "disabled";
  648. };
  649. usbc0: fusb302@22 {
  650. compatible = "fcs,fusb302";
  651. reg = <0x22>;
  652. interrupt-parent = <&gpio1>;
  653. interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
  654. pinctrl-names = "default";
  655. pinctrl-0 = <&usbc0_int>;
  656. vbus-supply = <&vbus5v0_typec0>;
  657. status = "okay";
  658. ports {
  659. #address-cells = <1>;
  660. #size-cells = <0>;
  661. port@0 {
  662. reg = <0>;
  663. usbc0_role_sw: endpoint@0 {
  664. remote-endpoint = <&dwc3_0_role_switch>;
  665. };
  666. };
  667. };
  668. usb_con0: connector {
  669. compatible = "usb-c-connector";
  670. label = "USB-C";
  671. data-role = "dual";
  672. power-role = "dual";
  673. try-power-role = "sink";
  674. op-sink-microwatt = <1000000>;
  675. sink-pdos =
  676. <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
  677. source-pdos =
  678. <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
  679. altmodes {
  680. #address-cells = <1>;
  681. #size-cells = <0>;
  682. altmode@0 {
  683. reg = <0>;
  684. svid = <0xff01>;
  685. vdo = <0xffffffff>;
  686. };
  687. };
  688. ports {
  689. #address-cells = <1>;
  690. #size-cells = <0>;
  691. port@0 {
  692. reg = <0>;
  693. usbc0_orien_sw: endpoint {
  694. remote-endpoint = <&usbdp_phy0_orientation_switch>;
  695. };
  696. };
  697. port@1 {
  698. reg = <1>;
  699. dp0_altmode_mux: endpoint {
  700. remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
  701. };
  702. };
  703. };
  704. };
  705. };
  706. };
  707. &i2c3 {
  708. status = "okay";
  709. //camera1
  710. };
  711. &i2c4 {
  712. status = "okay";
  713. pinctrl-0 = <&i2c4m1_xfer>;
  714. //camera2
  715. MPU6050: mpu6050@68 {
  716. compatible = "elfboard,mpu6050";
  717. reg = <0x68>;
  718. status = "okay";
  719. };
  720. };
  721. &i2c5 {
  722. status = "okay";
  723. pinctrl-names = "default";
  724. pinctrl-0 = <&i2c5m2_xfer>;
  725. ft5x06_dsi1: ft5x06@38 {
  726. compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
  727. reg = <0x38>;
  728. pinctrl-names = "ft5x06_defaults";
  729. pinctrl-0 = <&ft5x06_dsi2_gpio>;
  730. // interrupt-parent = <&gpio3>;
  731. // interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
  732. irq-gpio = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>;
  733. touchscreen-size-x = <1024>;
  734. touchscreen-size-y = <600>;
  735. status = "okay";
  736. };
  737. gt9xx_dsi1: gt9xx@14 {
  738. compatible = "goodix,gt911";
  739. reg = <0x14>;
  740. pinctrl-names = "gt9xx_default";
  741. pinctrl-0 = <&gt911_dsi2_gpio>;
  742. // interrupt-parent = <&gpio3>;
  743. // interrupts = <RK_PD3 IRQ_TYPE_EDGE_FALLING>;
  744. irq-gpio = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>;
  745. reset-gpio = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
  746. touchscreen-size-x = <1024>;
  747. touchscreen-size-y = <600>;
  748. is-mutex;
  749. filter-reg = <0x38>;
  750. bus-reg = <0x05>;
  751. status = "okay";
  752. };
  753. rtc: pcf8563@51 {
  754. compatible = "nxp,pcf8563";
  755. reg = <0x51>;
  756. status = "okay";
  757. };
  758. rx8010:rx8010@32 {
  759. compatible = "epson,rx8010";
  760. reg = <0x32>;
  761. status = "okay";
  762. };
  763. };
  764. &i2c7 {
  765. status = "okay";
  766. nau8822: nau8822@1a {
  767. status = "okay";
  768. #sound-dai-cells = <0>;
  769. compatible = "nuvoton,nau8822";
  770. reg = <0x1a>;
  771. clocks = <&mclkout_i2s0>;
  772. clock-names = "mclk";
  773. assigned-clocks = <&mclkout_i2s0>;
  774. assigned-clock-rates = <12288000>;
  775. pinctrl-names = "default";
  776. pinctrl-0 = <&i2s0_mclk>;
  777. };
  778. };
  779. &pcie2x1l0 {
  780. reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
  781. vpcie3v3-supply = <&vcc3v3_pcie20>;
  782. status = "okay";
  783. };
  784. &combphy0_ps {
  785. status = "okay";
  786. };
  787. &pcie2x1l2 {
  788. reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
  789. status = "okay";
  790. };
  791. &combphy1_ps {
  792. status = "okay";
  793. };
  794. &pcie30phy {
  795. rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>;
  796. status = "disabled";
  797. };
  798. &pcie3x4 {
  799. reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
  800. memory-region = <&dma_trans>;
  801. vpcie3v3-supply = <&vcc3v3_pcie30>;
  802. status = "disabled";
  803. };
  804. &pwm2 { //FAN
  805. status = "okay";
  806. };
  807. &pwm4 { //edp
  808. status = "okay";
  809. //pinctrl-name = "active";
  810. //pinctrl-0 = <&pwm4m0_pins>;
  811. };
  812. &pwm5 {//dsi0
  813. pinctrl-0 = <&pwm5m1_pins>;
  814. status = "okay";
  815. };
  816. &pwm6 {//dsi1
  817. status = "okay";
  818. };
  819. &hdmi0 {
  820. enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
  821. status = "disabled";
  822. };
  823. &hdmi0_in_vp0 {
  824. status = "disabled";
  825. };
  826. &hdptxphy_hdmi0 {
  827. status = "disabled";
  828. };
  829. &route_hdmi0 {
  830. status = "disabled";
  831. connect = <&vp0_out_hdmi0>;
  832. // force-output;
  833. // force_timing {
  834. // clock-frequency = <65000000>;
  835. // hactive = <1024>;
  836. // vactive = <768>;
  837. // hfront-porch = <24>;
  838. // hsync-len = <136>;
  839. // hback-porch = <160>;
  840. // vfront-porch = <3>;
  841. // vsync-len = <6>;
  842. // vback-porch = <29>;
  843. // hsync-active = <0>;
  844. // vsync-active = <0>;
  845. // de-active = <0>;
  846. // pixelclk-active = <0>;
  847. // };
  848. };
  849. &edp1 {
  850. force-hpd;
  851. status = "disabled";
  852. ports {
  853. port@1 {
  854. reg = <1>;
  855. edp_out_panel: endpoint {
  856. remote-endpoint = <&panel_in_edp1>;
  857. };
  858. };
  859. };
  860. };
  861. &route_edp1 {
  862. status = "disabled";
  863. connect = <&vp1_out_edp1>;
  864. };
  865. &route_dsi0 {
  866. status = "disabled";
  867. connect = <&vp3_out_dsi0>;
  868. };
  869. &dsi0 {
  870. status = "disabled";
  871. //rockchip,lane-rate = <1000>;
  872. dsi0_panel: panel@0 {
  873. status = "okay";
  874. // pinctrl-names = "default";
  875. // pinctrl-0 = <&mipi0_enable_gpio>;
  876. compatible = "simple-panel-dsi";
  877. reg = <0>;
  878. backlight = <&backlight_dsi0>;
  879. reset-delay-ms = <10>;
  880. enable-delay-ms = <10>;
  881. prepare-delay-ms = <10>;
  882. unprepare-delay-ms = <10>;
  883. disable-delay-ms = <60>;
  884. dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
  885. MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
  886. dsi,format = <MIPI_DSI_FMT_RGB888>;
  887. dsi,lanes = <4>;
  888. // enable-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
  889. // panel-init-sequence = [
  890. // ];
  891. // panel-exit-sequence = [
  892. // ];
  893. panel0_disp_timings0: display-timings {
  894. native-mode = <&panel0_7_1024x600>;
  895. panel0_7_1024x600: timings {
  896. hback-porch = <48>;
  897. hfront-porch = <40>;
  898. hactive = <1024>;
  899. hsync-len = <48>;
  900. vback-porch = <48>;
  901. vfront-porch = <40>;
  902. vactive = <600>;
  903. vsync-len = <4>;
  904. clock-frequency = <45000000>;
  905. vsync-active = <0>;
  906. hsync-active = <0>;
  907. de-active = <0>;
  908. pixelclk-active = <0>;
  909. };
  910. };
  911. ports {
  912. #address-cells = <1>;
  913. #size-cells = <0>;
  914. port@0 {
  915. reg = <0>;
  916. panel_in_dsi0: endpoint {
  917. remote-endpoint = <&dsi0_out_panel>;
  918. };
  919. };
  920. };
  921. };
  922. ports {
  923. #address-cells = <1>;
  924. #size-cells = <0>;
  925. port@1 {
  926. reg = <1>;
  927. dsi0_out_panel: endpoint {
  928. remote-endpoint = <&panel_in_dsi0>;
  929. };
  930. };
  931. };
  932. };
  933. /*
  934. * mipi_dcphy0 needs to be enabled
  935. * when dsi0 is enabled
  936. */
  937. &dsi0 {
  938. status = "disabled";
  939. };
  940. &dsi0_in_vp2 {
  941. status = "disabled";
  942. };
  943. &dsi0_in_vp3 {
  944. status = "disabled";
  945. };
  946. &dsi1 {
  947. status = "disabled";
  948. //rockchip,lane-rate = <1000>;
  949. dsi1_panel: panel@0 {
  950. status = "okay";
  951. compatible = "simple-panel-dsi";
  952. reg = <0>;
  953. backlight = <&backlight_dsi1>;
  954. reset-delay-ms = <10>;
  955. enable-delay-ms = <10>;
  956. prepare-delay-ms = <10>;
  957. unprepare-delay-ms = <10>;
  958. disable-delay-ms = <10>;
  959. dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
  960. MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
  961. dsi,format = <MIPI_DSI_FMT_RGB888>;
  962. dsi,lanes = <4>;
  963. // enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
  964. // panel-init-sequence = [
  965. // ];
  966. // panel-exit-sequence = [
  967. // ];
  968. panel1_disp_timings1: display-timings {
  969. native-mode = <&panel1_7_1024x600>;
  970. panel1_7_1024x600: timings {
  971. hback-porch = <48>;
  972. hfront-porch = <40>;
  973. hactive = <1024>;
  974. hsync-len = <48>;
  975. vback-porch = <48>;
  976. vfront-porch = <40>;
  977. vactive = <600>;
  978. vsync-len = <4>;
  979. clock-frequency = <45000000>;
  980. vsync-active = <0>;
  981. hsync-active = <0>;
  982. de-active = <0>;
  983. pixelclk-active = <0>;
  984. };
  985. };
  986. ports {
  987. #address-cells = <1>;
  988. #size-cells = <0>;
  989. port@0 {
  990. reg = <0>;
  991. panel_in_dsi1: endpoint {
  992. remote-endpoint = <&dsi1_out_panel>;
  993. };
  994. };
  995. };
  996. };
  997. ports {
  998. #address-cells = <1>;
  999. #size-cells = <0>;
  1000. port@1 {
  1001. reg = <1>;
  1002. dsi1_out_panel: endpoint {
  1003. remote-endpoint = <&panel_in_dsi1>;
  1004. };
  1005. };
  1006. };
  1007. };
  1008. &i2s0_8ch {
  1009. status = "okay";
  1010. pinctrl-0 = <&i2s0_lrck
  1011. &i2s0_sclk
  1012. &i2s0_sdi0
  1013. &i2s0_sdo0>;
  1014. };
  1015. &i2s5_8ch {
  1016. status = "okay";
  1017. };
  1018. &i2s7_8ch {
  1019. status = "okay";
  1020. };
  1021. &sdhci {
  1022. bus-width = <8>;
  1023. no-sdio;
  1024. no-sd;
  1025. non-removable;
  1026. max-frequency = <200000000>;
  1027. mmc-hs400-1_8v;
  1028. mmc-hs400-enhanced-strobe;
  1029. status = "okay";
  1030. };
  1031. &sdmmc {
  1032. max-frequency = <150000000>;
  1033. no-sdio;
  1034. no-mmc;
  1035. bus-width = <4>;
  1036. cap-mmc-highspeed;
  1037. cap-sd-highspeed;
  1038. disable-wp;
  1039. sd-uhs-sdr104;
  1040. vqmmc-supply = <&vccio_sd_s0>;
  1041. cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
  1042. status = "okay";
  1043. };
  1044. &u2phy0 {
  1045. status = "okay";
  1046. };
  1047. &u2phy1 {
  1048. status = "okay";
  1049. };
  1050. &u2phy2 {
  1051. status = "okay";
  1052. };
  1053. &u2phy3 {
  1054. status = "okay";
  1055. };
  1056. &u2phy0_otg {
  1057. status = "okay";
  1058. };
  1059. &u2phy1_otg {
  1060. phy-supply = <&vbus5v0_typec1>;
  1061. status = "okay";
  1062. };
  1063. &u2phy2_host {
  1064. status = "okay";
  1065. };
  1066. &u2phy3_host {
  1067. status = "okay";
  1068. };
  1069. &usb_host0_ehci {
  1070. status = "okay";
  1071. };
  1072. &usb_host0_ohci {
  1073. status = "okay";
  1074. };
  1075. &usb_host1_ehci {
  1076. status = "okay";
  1077. };
  1078. &usb_host1_ohci {
  1079. status = "okay";
  1080. };
  1081. &usbdp_phy0 {
  1082. status = "okay";
  1083. orientation-switch;
  1084. rockchip,dp-lane-mux = <2 3>;
  1085. svid = <0xff01>;
  1086. sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
  1087. sbu2-dc-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
  1088. port {
  1089. #address-cells = <1>;
  1090. #size-cells = <0>;
  1091. usbdp_phy0_orientation_switch: endpoint@0 {
  1092. reg = <0>;
  1093. remote-endpoint = <&usbc0_orien_sw>;
  1094. };
  1095. usbdp_phy0_dp_altmode_mux: endpoint@1 {
  1096. reg = <1>;
  1097. remote-endpoint = <&dp0_altmode_mux>;
  1098. };
  1099. };
  1100. };
  1101. &usbdp_phy0_dp {
  1102. status = "okay";
  1103. };
  1104. &usbdp_phy0_u3 {
  1105. status = "okay";
  1106. };
  1107. &usbdrd3_0 {
  1108. status = "okay";
  1109. };
  1110. &usbdrd_dwc3_0 {
  1111. dr_mode = "otg";
  1112. usb-role-switch;
  1113. status = "okay";
  1114. port {
  1115. #address-cells = <1>;
  1116. #size-cells = <0>;
  1117. dwc3_0_role_switch: endpoint@0 {
  1118. reg = <0>;
  1119. remote-endpoint = <&usbc0_role_sw>;
  1120. };
  1121. };
  1122. };
  1123. &usbdp_phy1 {
  1124. status = "okay";
  1125. rockchip,dp-lane-mux = <2 3>;
  1126. };
  1127. &usbdp_phy1_dp {
  1128. status = "okay";
  1129. };
  1130. &usbdp_phy1_u3 {
  1131. status = "okay";
  1132. };
  1133. &usbdrd3_1 {
  1134. status = "okay";
  1135. };
  1136. &usbdrd_dwc3_1 {
  1137. status = "okay";
  1138. dr_mode = "host";
  1139. };
  1140. &usbhost3_0 {
  1141. status = "okay";
  1142. };
  1143. &usbhost_dwc3_0 {
  1144. status = "okay";
  1145. };
  1146. &combphy2_psu {
  1147. status = "okay";
  1148. };
  1149. /* Should work with at least 128MB cma reserved above. */
  1150. &hdmirx_ctrler {
  1151. status = "okay";
  1152. #sound-dai-cells = <1>;
  1153. pinctrl-names = "default";
  1154. pinctrl-0 = <&hdmim2_rx_cec &hdmim2_rx_hpdin &hdmim2_rx_scl &hdmim2_rx_sda &hdmirx_det_gpio>;
  1155. /* Effective level used to trigger HPD: 0-low, 1-high */
  1156. hpd-trigger-level = <1>;
  1157. hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
  1158. };
  1159. &av1d_mmu {
  1160. status = "okay";
  1161. };
  1162. &cpu_l0 {
  1163. cpu-supply = <&vdd_cpu_lit_s0>;
  1164. mem-supply = <&vdd_cpu_lit_mem_s0>;
  1165. };
  1166. &cpu_b0 {
  1167. cpu-supply = <&vdd_cpu_big0_s0>;
  1168. mem-supply = <&vdd_cpu_big0_mem_s0>;
  1169. };
  1170. &cpu_b2 {
  1171. cpu-supply = <&vdd_cpu_big1_s0>;
  1172. mem-supply = <&vdd_cpu_big1_mem_s0>;
  1173. };
  1174. &gpu {
  1175. mali-supply = <&vdd_gpu_s0>;
  1176. mem-supply = <&vdd_gpu_mem_s0>;
  1177. status = "okay";
  1178. };
  1179. &iep {
  1180. status = "okay";
  1181. };
  1182. &iep_mmu {
  1183. status = "okay";
  1184. };
  1185. &jpegd {
  1186. status = "okay";
  1187. };
  1188. &jpegd_mmu {
  1189. status = "okay";
  1190. };
  1191. &jpege_ccu {
  1192. status = "okay";
  1193. };
  1194. &jpege0 {
  1195. status = "okay";
  1196. };
  1197. &jpege0_mmu {
  1198. status = "okay";
  1199. };
  1200. &jpege1 {
  1201. status = "okay";
  1202. };
  1203. &jpege1_mmu {
  1204. status = "okay";
  1205. };
  1206. &jpege2 {
  1207. status = "okay";
  1208. };
  1209. &jpege2_mmu {
  1210. status = "okay";
  1211. };
  1212. &jpege3 {
  1213. status = "okay";
  1214. };
  1215. &jpege3_mmu {
  1216. status = "okay";
  1217. };
  1218. &mpp_srv {
  1219. status = "okay";
  1220. };
  1221. &rga3_core0 {
  1222. status = "okay";
  1223. };
  1224. &rga3_0_mmu {
  1225. status = "okay";
  1226. };
  1227. &rga3_core1 {
  1228. status = "okay";
  1229. };
  1230. &rga3_1_mmu {
  1231. status = "okay";
  1232. };
  1233. &rga2 {
  1234. status = "okay";
  1235. };
  1236. &rknpu {
  1237. rknpu-supply = <&vdd_npu_s0>;
  1238. mem-supply = <&vdd_npu_mem_s0>;
  1239. status = "okay";
  1240. };
  1241. &rknpu_mmu {
  1242. status = "okay";
  1243. };
  1244. &rkvdec_ccu {
  1245. status = "okay";
  1246. };
  1247. &rkvdec0 {
  1248. status = "okay";
  1249. };
  1250. &rkvdec0_mmu {
  1251. status = "okay";
  1252. };
  1253. &rkvdec1 {
  1254. status = "okay";
  1255. };
  1256. &rkvdec1_mmu {
  1257. status = "okay";
  1258. };
  1259. &rkvenc_ccu {
  1260. status = "okay";
  1261. };
  1262. &rkvenc0 {
  1263. status = "okay";
  1264. };
  1265. &rkvenc0_mmu {
  1266. status = "okay";
  1267. };
  1268. &rkvenc1 {
  1269. status = "okay";
  1270. };
  1271. &rkvenc1_mmu {
  1272. status = "okay";
  1273. };
  1274. &rockchip_suspend {
  1275. status = "okay";
  1276. rockchip,sleep-debug-en = <1>;
  1277. };
  1278. &saradc {
  1279. status = "okay";
  1280. vref-supply = <&vcc_1v8_s0>;
  1281. };
  1282. &tsadc {
  1283. status = "okay";
  1284. };
  1285. &vdpu {
  1286. status = "okay";
  1287. };
  1288. &vdpu_mmu {
  1289. status = "okay";
  1290. };
  1291. &vop {
  1292. status = "okay";
  1293. };
  1294. &vop_mmu {
  1295. status = "okay";
  1296. };
  1297. /* vp0 & vp1 splice for 8K output */
  1298. &vp0 {
  1299. rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>;
  1300. rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>;
  1301. };
  1302. &vp1 {
  1303. rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>;
  1304. rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>;
  1305. };
  1306. &vp2 {
  1307. rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>;
  1308. rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>;
  1309. };
  1310. &vp3 {
  1311. rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>;
  1312. rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART3>;
  1313. };
  1314. &wdt {
  1315. status = "okay";
  1316. };